1. Field of the Invention
The present invention relates to a semiconductor device test method using an evaluation LSI and, more specifically, to a semiconductor device test method of measuring the amount of noise generated in a semiconductor device.
The present invention also relates to technique for testing whether or not the oscillation period of clock signal is within a predetermined range.
2. Description of the Related Art
LSIs have been developing in recent years, to attain a higher-speed operation and a higher integration. This development has involved the problem of erroneous operation due to the internal noise of LSIs. Hence, evaluation of influence of internal noise of LSIs has become more significant. Internal noise of LSIs is conventionally evaluated as follows. Power source pins and ground pins, for example, are formed as monitoring package pins connected to internal pads in the LSI. A probe is used for the monitoring pins, and monitoring is carried out by use of an oscilloscope or the like receiving test result signals from the probe. That is, internal noise of the LSI is evaluated by directly measuring the noise inside the LSI. Also in case of testing oscillation condition of a clock generation circuit, a monitoring pin is provided, and a clock signal is monitored by an oscilloscope or the like.
A technique concerning a semiconductor test device is described in Patent Publication JP-A-2000-97996. FIG. 8 shows the configuration of the clock-period monitoring circuit described in this publication. The clock-period monitoring circuit is used to detect an input clock signal having an oscillation period shorter than a reference period. The delay time of a fixed-delay circuit 52 is set equal to a width of a clock pulse during which the clock signal assumes a H-level. The delay time of a variable-delay circuit 54 is set equal to a value expressed by the reference period minus double the delay time of the fixed-delay circuit. Assume, for example, the case of detecting that pulse width of the clock signal is 4 ns (nanosecond) and the oscillation period of the clock signal has decreased to 24 ns or lower. In this case, the delay time of the fixed-delay circuit 52 is set at 4 ns, and the delay time of the variable-delay circuit 54 is set at (24 ns−4 ns×2)=16 ns.
A flip-flop 51 shifts the output signal 51A thereof to a H-level in synchrony with a pulse of the clock signal. The fixed-delay circuit 52 delays the output signal 51A of the flip-flop 51, and outputs a signal 53A through a gate circuit 53. An AND gate 56 outputs a logical product of the clock signal and the output signal 53A of the fixed-delay circuit 52. The variable-delay circuit 54 further delays the signal 53A output form the fixed-delay circuit 52, and outputs a signal 54A. A clock terminal of the flip-flop 51 is fed with the output signal 54A of the variable-delay circuit 54. When the signal 54A shifts to a H-level, a signal of L-level is then output. The output signal 51A which has thus shifted to a L-level is delayed by the fixed-delay circuit 52, and is further input to one of input terminals of the AND gate 56 through the gate circuit 53.
Consideration will now be taken in the case that two consecutive pulses of the clock signal are input thereto. Upon input of the first pulse, the output signal 51A of the flip-flop 51 shifts to a H-level. This output signal 51A is delayed during a H-level period of the clock signal in the fixed-delay circuit 52. Therefore, both of inputs to the AND gate 56 cannot assume a H-level at a time. The flip-flop 51 outputs the output signal 51A at a L-level after the delay time of the fixed-delay circuit 52 plus the delay time of the variable-delay circuit 54, i.e., the reference period minus the delay time of the fixed-delay circuit 52 is elapsed since the time instant at which the first pulse of the clock signal is input. This output signal 51A is delayed by the fixed-delay circuit 52, and input to one of the input terminals of the AND gate 56. By this operation, the signal 53A input to the one of the input terminals of the AND gate 56 shifts to a L-level after a time period corresponding to the reference period is elapsed since the time instant at which the first pulse of the clock signal is input.
If the period of the clock signal is longer than the reference period, the output signal 53A of the fixed-delay circuit 52 assumes a L-level when the second pulse of the clock signal is input. Thus, both inputs to the AND gate 56 cannot assume a H-level at a time. On the other hand, if the period of the clock signal is shorter than the reference period, the second pulse of the clock signal is input before the signal 53A shifts to a L-level. Therefore, the AND gate 56 outputs a signal at a H-level. According to this operation, the clock-period monitoring circuit 50 outputs a defective-clock detection signal if the period of the clock signal exceeds the period corresponding to the maximum operation frequency in a specific mode of test. The publication JP-A-2000-97996 recites that execution of tests can be prevented by using the clock-period monitoring circuit under the condition that the clock signal input to the semiconductor device being tested (DUT: Device Under Test) exceeds the predetermined value.
In the conventional test method, internal lines are connected to external terminals, and probes are used for the external terminals to measure the noise inside the semiconductor device. However, as LSIs have achieved a higher speed, accurate measurement of noise inside the semiconductor device have become difficult due to various factors such as LSI package noise, accuracy of measurement devices, etc. Also in case of inspecting oscillation condition of a clock generation circuit by providing a monitoring pin, the higher speed causes difficulties in accurate measurement.
There may be considered another method of inputting a reference clock or sampling clock to a semiconductor device, without providing the monitoring pin during testing the clock signal. In this case, however, a problem arises in that the LSI has a complicated structure because circuits for generating those clocks and external connection pins for inputting the clocks to the semiconductor device must be further provided.
In the technique of JP-A-2000-97996, the clock signal input to the semiconductor device is monitored by the clock-period monitoring circuit 50. If the period of the clock signal is shorter than the predetermined period, the failure of the clock signal is detected. In this publication, however, the clock-period monitoring circuit 50 is used to prevent erroneous operation of a semiconductor test device, i.e., the circuit 50 merely detects a state that the period of the clock signal is shorter than the predetermined period. If the period of the clock signal is longer, the failure of the clock signal cannot be detected.